1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a semiconductor apparatus with TSVs (through-silicon vias).
2. Related Art
Capacities and speeds of semiconductor memories, which are used as memory devices in most electronic systems, have steadily increased. Various attempts have been made to mount a memory with increased capacity within a smaller area and drive the memory efficiently.
In order to improve the degree of integration of semiconductor memories, a three-dimensional (3D) layout, in which a plurality of memory chips is stacked, has been adopted in place of the existing two-dimensional (2D) layout. As memories trend toward higher integration and higher capacity, the 3-D layout is being used more to increase the capacity and decrease the size of a semiconductor memory devices.
A TSV (through-silicon via) type has been used in the 3D layout structure. The TSV type has been adopted as an alternative for overcoming degradation of a transmission speed due to a distance to a controller on a module, poor data bandwidth, and degradation of a transmission speed due to variables in a package. In the TSV type, paths are defined to pass through a plurality of memory chips, and electrodes are formed in the paths so that respective memory chips and a controller can communicate with each other. In a stacked semiconductor memory apparatus to which the TSV type is applied, wires, sub packages and package balls, which are used in an SIP type and a POP type, are not needed, and electrodes are connected directly over a controller in such a way as to have paths which pass is through a plurality of memory chips. Bumps are formed between the paths which pass through the plurality of memory chips, to electrically connect the plurality of memory chips to each other and to a controller.
FIG. 1 is a schematic cross-sectional view explaining processing errors that may occur when forming TSVs in a semiconductor device.
FIG. 1 shows a metal layer 10 for forming a TSV, a dielectric layer 20, and a wafer layer 30.
While not shown in FIG. 1, connection layers (not shown) may be electrically connected to the upper and lower ends of the metal layer 10.
The connection layers are formed of a conductive substance for connecting the TSV with another TSV or a controller. In general, the connection layers are constituted by bumps.
(a) of FIG. 1 shows the case in which the TSV is normally formed in a semiconductor chip.
Referring to (a) of FIG. 1, a path is defined to pass through the wafer layer 30, and the metal layer 10 made of a metallic substance is normally formed in the path.
In the TSV, in order to isolate the metal layer 10 and the wafer layer 30 from each other, the dielectric layer 20 such as an oxide is formed between the metal layer 10 and the wafer layer 30.
(b) and (c) of FIG. 1 show the cases in which the metal layer 10 is abnormally formed in the path surrounded by the dielectric layer 20.
If a variation occurs in process conditions for forming the TSV, the metal layer 10 may be abnormally formed in the course of filling the metal layer 10 in the path surrounded by the dielectric layer 20.
In the event that the metal layer 10 is formed with an open type gap as shown in (b) of FIG. 1, a current path is not created between an electrode e1 and an electrode e2. Therefore, the TSV formed as in (b) of FIG. 1 cannot transfer a signal.
In the event that the metal layer 10 is formed with a void type gap as shown in (c) of FIG. 1, although a current path is created between an electrode e3 and an electrode e4, the current path has a large resistance value due to the presence of the void type gap. Therefore, the TSV formed as in (c) of FIG. 1 cannot stably transfer a signal.
FIG. 2 is a schematic cross-sectional view explaining processing errors that may occur when connecting chips formed with TSVs.
Referring to FIG. 2, a first chip 201 and a second chip 202 are formed with three TSVs are connected with each other. Bumps 203 are formed on both ends of the TSVs of the respective chips 201 and 202 to be electrically connected with the TSVs.
(d) of FIG. 2 shows the case in which bumps to be connected with the TSVs are normally formed such that the TSV of the first chip 201 and the TSV of the second chip 202 are normally connected with each other.
Referring to (d) of FIG. 2, it is shown that a bump 203-1 connected to the TSV of the first chip 201 and a bump 203-2 connected to the TSV of the second chip 202 are normally connected with each other.
Hence, the TSV of the first chip 201 and the TSV of the second chip 202 formed as shown in (d) of FIG. 2 are electrically connected with each other and can communicate normally with each other.
(e) and (f) of FIG. 2 show that bumps connected to TSVs are abnormally formed so that processing error occur.
Referring to (e) of FIG. 2, a bump 203-4 connected to the TSV of the second chip 202 is abnormally formed by being shifted.
Hence, a bump 203-3 connected to the TSV of the first chip 201 and the bump 203-4 connected to the TSV of the second chip 202 may not be electrically connected with each other, or even when they are electrically connected with each other, they cannot normally implement signal communication due to high resistance from the offset bumps 203-3 and 203-4.
Referring to (f) of FIG. 2, it is shown that a bump is not formed on the TSV of the second chip 202.
Hence, since a bump 203-5 connected to the TSV of the first chip 201 cannot be electrically connected with the TSV of the second chip 202, signal communication can not be implemented.
As can be seen from FIGS. 1 and 2, a processing error may be caused in the course of forming TSVs in semiconductor chips or connecting a plurality of chips formed with TSVs with one another.
If a subsequent process is continuously performed for a product in which the processing error is caused in the course of forming TSVs in semiconductor chips or connecting a plurality of chips formed with TSVs with one another, the manufacturing yield decreases, the productivity deteriorates, and additional costs are incurred.